Electronic Design

DFT Propels SoC IC Testing

The Design-for-Test (DFT) methodology is a strong driving force in the cost-effective testing of large-volume commodity items with very short life cycles, like system-on-chip (SoC) devices. It will ...
Semiconductor Engineering

Multi-die Testing In The Field Must Build On Established Test Methodologies

The AI revolution is significantly outpacing the IC industry’s ability to sufficiently test multi-chip systems for all necessary failure mechanisms at probe, final test, and system-level test. The ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
EDN

Is DFT ready for prime time?

Over the last few years, design-for-test (DFT) chip-testing techniques such as internal scan (ISCAN), automatic test-pattern generation (ATPG), built-in self-test (BIST), and boundary scan (BSCAN) ...
TCTMD

PRAETORIAN-DFT: Safe to Forgo Defibrillation Testing for S-ICD Implant

CHICAGO, IL—Defibrillation testing (DFT) is not always necessary in patients receiving a subcutaneous implantable cardioverter defibrillator (S-ICD) when using a scoring system that assesses the ...
Semiconductor Engineering

AI Testing: Pushing Beyond DFT Architectures

Every day, more applications are deploying artificial intelligence (AI) system to increase automation beyond traditional systems. The continuous growth in computing demands of AI systems require ...