Optical phase-locked loops (OPLLs) are closed-loop control systems that stabilise and synchronise the phase of a slave laser with respect to a reference source, enabling coherent optical generation ...

But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing its output by 100 will give you a signal you can lock to a 1 MHz crystal oscillator which is, of course, trivial to build.

This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...

When Hackaday runs a contest, we see all manner of clever projects. But inevitably there are some we don’t see, because their builders didn’t manage to get them finished in time. [Park Frazer]’s phase ...

The NB4N507A is a fully integrated phase lock loop (PLL) designed to replace expensive crystal oscillators for clock generation in a variety of consumer and networking applications. The IC generates a ...

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles ...

The purpose of a phase locked loop (PLL) is to generate a frequency and phase-locked output oscillation signal. To achieve this goal, prior art essentially functioned ...

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...

Whilst poring over 4046 phase locked loop data sheets, I noticed yet another subtle useful difference between the the later faster 74HC4046 (diag from NXP data sheet) and the earlier slower CD4046.

I had never heard of the 74HCT9046 phase-locked loop before a fortnight ago, and now I own one. To my shame, it was apparently released by Phillips (now Nexperia) around 20 years ago – that said, the ...