The Altera JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to or from the FPGA devices. The JESD204B ...
Munich, Germany — Infineon Technologies AG has added a floating-point maths unit (FPU) to its library of system design blocks supporting the TriCore processor core. The addition of an FPU will improve ...
On a dual-core processor, you can entirely disable the second core through the System Configuration menu or partially disable it using processor affinity options. System Configuration lets you set how ...
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