IEEE

Design Landscape of VVC Binary Arithmetic Decoder using Multiple Bypass Bins Processing

Abstract: The striking video consumption nowadays has never been higher. Thus, this burdensome situation affects the limited bandwidth to transmit this kind of data. With that in mind, video codecs ...
IEEE

FPGA Architectures for 32-Point Radix-2 DIT and DIF FFT Using IEEE 754 Half-Precision ...

Abstract: This paper presents the design and FPGA implementation of a 32-point Radix-2 Fast Fourier Transform (FFT) using IEEE-754 half-precision (FP16) floating-point arithmetic. Both ...