English
全部
搜索
图片
视频
短视频
地图
资讯
更多
购物
航班
旅游
笔记本
报告不当内容
请选择下列任一选项。
无关
低俗内容
成人
儿童性侵犯
Verilog
Complete Tutorial
Verilog Tutorial
Verilog Coding
SystemVerilog Complete Course
Verilog Tutorial
for Beginners
Time Scale
Verilog
Verilog
HDL
How to Write Verilog
Code in Quartus
Verilog
Codes
Learn Verilog
Curs Complet
Verilog
Programming
What Is an Accumulator
Verilog
Verilator
Verilog
for Beginers One Shot
Verilog
Verilog
for Beginners
Verilog
for Loop
Verilog
Basics
Xilinx
Verilog
Verilog
HDL Tutorial
Verilog
Code
Verilog
Programming Tutorial
Verilog
Introduction
Verilog
Alu
Verilog Coding
Quartus
Verilog
Advanced Tutorial
SystemVerilog
Tutorials
Verilog
NPTEL
Verilog Tutorial
Vivado
Icarus Verilog
Installation
时长
全部
短(小于 5 分钟)
中(5-20 分钟)
长(大于 20 分钟)
日期
全部
过去 24 小时
过去一周
过去一个月
去年
清晰度
全部
低于 360p
360p 或更高
480p 或更高
720p 或更高
1080p 或更高
源
全部
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
价格
全部
免费
付费
清除筛选条件
安全搜索:
中等
严格
中等(默认)
关闭
筛选器
Verilog
Complete Tutorial
Verilog Tutorial
Verilog Coding
SystemVerilog Complete Course
Verilog Tutorial
for Beginners
Time Scale
Verilog
Verilog
HDL
How to Write Verilog
Code in Quartus
Verilog
Codes
Learn Verilog
Curs Complet
Verilog
Programming
What Is an Accumulator
Verilog
Verilator
Verilog
for Beginers One Shot
Verilog
Verilog
for Beginners
Verilog
for Loop
Verilog
Basics
Xilinx
Verilog
Verilog
HDL Tutorial
Verilog
Code
Verilog
Programming Tutorial
Verilog
Introduction
Verilog
Alu
Verilog Coding
Quartus
Verilog
Advanced Tutorial
SystemVerilog
Tutorials
Verilog
NPTEL
Verilog Tutorial
Vivado
Icarus Verilog
Installation
Verilog
Training
Verilog
Projects
1:24
YouTube
Cadence Design Systems
Difference between Data types of Verilog and SystemVerilog #cadence #chipdesign
SystemVerilog improves upon Verilog by offering richer data types and powerful object‑oriented features. With support for clearer data representation, arrays, structs, enums, and OOP concepts like encapsulation, inheritance, and polymorphism, SystemVerilog enables cleaner, more scalable, and reusable code for both design and verification.# ...
已浏览 962 次
3 周前
短视频
0:49
已浏览 3966 次
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially
engcalebj28
2:31
已浏览 110 次
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
Chip Logic Studio
Verilog Tutorial
9:21
Learn Verilog from Scratch
YouTube
Silicon Glyph
已浏览 124 次
3 个月之前
1:08:06
Mastering Verilog in 1 Hour 🚀: A Complete Guide to Key Concepts | Beginners to Advanced
YouTube
Explore VLSI
已浏览 9.3万 次
2025年3月9日
2:58
Verilog Day 1: Introduction and Data Types Explained from Scratch
YouTube
Chip Logic Studio
已浏览 270 次
7 个月之前
热门视频
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
YouTube
Chip Logic Studio
已浏览 678 次
2 个月之前
0:59
Verilog lecture 1 || Verilog HDL by Samir palnitkar || || How to learn Verilog #verilog
YouTube
Aditya Singh
已浏览 237 次
1 个月前
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
YouTube
Cadence Design Systems
已浏览 1894 次
4 周前
Verilog Examples
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
YouTube
Chip Logic Studio
已浏览 163 次
2 个月之前
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
YouTube
Chip Logic Studio
已浏览 87 次
2 个月之前
2:41
conditional statements in verilog | if else & case
YouTube
Chip Logic Studio
已浏览 174 次
3 个月之前
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 678 次
2 个月之前
YouTube
Chip Logic Studio
0:59
Verilog lecture 1 || Verilog HDL by Samir palnitkar || || How to learn Verilog #verilog
已浏览 237 次
1 个月前
YouTube
Aditya Singh
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
已浏览 1894 次
4 周前
YouTube
Cadence Design Systems
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 110 次
1 个月前
YouTube
Chip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 163 次
2 个月之前
YouTube
Chip Logic Studio
2:55
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
已浏览 101 次
2 个月之前
YouTube
Chip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 87 次
2 个月之前
YouTube
Chip Logic Studio
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 116 次
1 个月前
YouTube
Chip Logic Studio
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
已浏览 1519 次
2 个月之前
YouTube
Chip Logic Studio
2:41
conditional statements in verilog | if else & case
已浏览 174 次
3 个月之前
YouTube
Chip Logic Studio
1:24
Addition in verilog || Verilog coding techniques part 17 #vlsi #allaboutvlsi #digitaldesign
已浏览 1908 次
1 个月前
YouTube
ALL ABOUT VLSI
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a search engine for recruiters—if your profile doesn’t have the right keywords, you won’t be found or considered for interviews. To fix this, you need to: 🔑 Target Keywords: Add technical skills like (ex. Python, Verilog, or UVM) to your headline, about section, and experience. 🖼️ Build a Portfolio: Don’t just list skills—post photos of your hardware builds or screen recordings of your code. 📄 Pin Your Resume
已浏览 3966 次
4 个月之前
TikTok
engcalebj28
Servomotor con FPGA NANO 1k: Proyecto Mecatrónico
已浏览 6245 次
10 个月之前
TikTok
fpgaedudesign
0:35
FPGAs Peruanas: Prototipo Oficial y Entrenamiento
已浏览 1.1万 次
2024年11月12日
TikTok
capsula.electronica
0:10
4 fpga stratosky rumbo a Mexico #Stratosky #verilog #systemverilog #fpga #vhdl
已浏览 1630 次
4 个月之前
TikTok
capsula.electronica
Lộ Trình 6 Bước Trở Thành Kỹ Sư Thiết Kế IC
已浏览 4660 次
2025年4月25日
TikTok
chiptalkglobal
0:16
Cansados pero felices ,salieron 50 nuevas unidades de placas FPGAs StratoSky para Latam ,gracias Dios por la bendición #verilog #fpgas #systemverilog #Stratosky #vhdl
已浏览 1357 次
2 个月之前
TikTok
capsula.electronica
1:00
Led blinking using verilog || Verilog coding techniques part - 10|| All about VLSI ||
已浏览 2227 次
1 个月前
YouTube
ALL ABOUT VLSI
1:56
You NEED a polished and ATS-friendly resume in 2026……. A resume is essentially your first impression with recruiters if yours isn’t optimized with the right structure and keywords, you won’t even make it past the initial screening. To fix this, you need to: 🔑 Use LaTeX: Don’t just use a basic doc!! Templates like Jake’s Resume on Overleaf are highly compatible with ATS and look professional to recruiters. 🖼️ Showcase Projects: Don’t just list titles provide links to your GitHub or portfolios s
已浏览 1253 次
4 个月之前
TikTok
engcalebj28
展开
更多类似内容
短视频
1:24
Difference between Data types of Verilog and SystemVerilog #cadence #chipdesign
已浏览 962 次
3 周前
YouTube
Cadence Design Systems
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginner
已浏览 678 次
2 个月之前
YouTube
Chip Logic Studio
0:59
Verilog lecture 1 || Verilog HDL by Samir palnitkar || || How to learn Verilog #verilog
已浏览 237 次
1 个月前
YouTube
Aditya Singh
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
已浏览 1894 次
4 周前
YouTube
Cadence Design Systems
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a
已浏览 3966 次
4 个月之前
TikTok
engcalebj28
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 110 次
1 个月前
YouTube
Chip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginner
已浏览 163 次
2 个月之前
YouTube
Chip Logic Studio
2:55
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
已浏览 101 次
2 个月之前
YouTube
Chip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginner
已浏览 87 次
2 个月之前
YouTube
Chip Logic Studio
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 116 次
1 个月前
YouTube
Chip Logic Studio
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
已浏览 1519 次
2 个月之前
YouTube
Chip Logic Studio
2:41
conditional statements in verilog | if else & case
已浏览 174 次
3 个月之前
YouTube
Chip Logic Studio
1:24
Addition in verilog || Verilog coding techniques part 17 #vlsi #allaboutvlsi #digitaldesign
已浏览 1908 次
1 个月前
YouTube
ALL ABOUT VLSI
Servomotor con FPGA NANO 1k: Proyecto Mecatrónico
已浏览 6245 次
10 个月之前
TikTok
fpgaedudesign
0:35
FPGAs Peruanas: Prototipo Oficial y Entrenamiento
已浏览 1.1万 次
2024年11月12日
TikTok
capsula.electronica
0:10
4 fpga stratosky rumbo a Mexico #Stratosky #verilog #systemverilog #fpga #vhdl
已浏览 1630 次
4 个月之前
TikTok
capsula.electronica
Lộ Trình 6 Bước Trở Thành Kỹ Sư Thiết Kế IC
已浏览 4660 次
2025年4月25日
TikTok
chiptalkglobal
0:16
Cansados pero felices ,salieron 50 nuevas unidades de placas FPGAs StratoSky para Latam
已浏览 1357 次
2 个月之前
TikTok
capsula.electronica
1:00
Led blinking using verilog || Verilog coding techniques part - 10|| All about VLSI ||
已浏览 2227 次
1 个月前
YouTube
ALL ABOUT VLSI
1:56
You NEED a polished and ATS-friendly resume in 2026……. A resume is
已浏览 1253 次
4 个月之前
TikTok
engcalebj28
更多类似内容
反馈