English
全部
搜索
图片
视频
短视频
地图
资讯
更多
购物
航班
旅游
笔记本
报告不当内容
请选择下列任一选项。
无关
低俗内容
成人
儿童性侵犯
Verilog Tutorial
Verilog
vs VHDL
SystemVerilog
Verilog
HDL Tutorial
SystemVerilog Vivado
Tutorial
VHDL
SystemVerilog
Tutorials
Verilator
HDL Coder
Verilog
Palnitkar Tutorials
Verilog
Code for Alu
Verilog
HDL
Verilog
Code for Avalon Streaming
Verilog
Projects
SystemVerilog Academy
Verilog
Examples
MIPS Processor
Verilog
Coding
FPGA
Verilog
Verilog
Interview Questions
Quartus II
Verilog
for Beginners
ModelSim
RISC-V
Xilinx ISE
Verilog
Simulator
Verilog
Basics
ASIC
时长
全部
短(小于 5 分钟)
中(5-20 分钟)
长(大于 20 分钟)
日期
全部
过去 24 小时
过去一周
过去一个月
去年
清晰度
全部
低于 360p
360p 或更高
480p 或更高
720p 或更高
1080p 或更高
源
全部
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
价格
全部
免费
付费
清除筛选条件
安全搜索:
中等
严格
中等(默认)
关闭
筛选器
Verilog Tutorial
Verilog
vs VHDL
SystemVerilog
Verilog
HDL Tutorial
SystemVerilog Vivado
Tutorial
VHDL
SystemVerilog
Tutorials
Verilator
HDL Coder
Verilog
Palnitkar Tutorials
Verilog
Code for Alu
Verilog
HDL
Verilog
Code for Avalon Streaming
Verilog
Projects
SystemVerilog Academy
Verilog
Examples
MIPS Processor
Verilog
Coding
FPGA
Verilog
Verilog
Interview Questions
Quartus II
Verilog
for Beginners
ModelSim
RISC-V
Xilinx ISE
Verilog
Simulator
Verilog
Basics
ASIC
2:52
YouTube
Chip Logic Studio
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners Welcome to Chip Logic Studio (CLS) 🚀 In this video, we learn how to design a Counter in Verilog HDL, write a complete Testbench, and perform RTL Simulation step by step. This tutorial is perfect for beginners in VLSI, Digital Design, and Verilog Programming ...
已浏览 678 次
2 个月之前
短视频
0:25
已浏览 161 次
Want to know how a 7-segment HEX display works on an FPGA? 🔢 In this short
chipcraftfpga
1:03
已浏览 1907 次
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
Cadence Design Systems
Verilog Basics
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
YouTube
Chip Logic Studio
已浏览 100 次
2 个月之前
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
YouTube
Chip Logic Studio
已浏览 116 次
2 个月之前
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
YouTube
Chip Logic Studio
已浏览 83 次
2 个月之前
热门视频
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
YouTube
Chip Logic Studio
已浏览 164 次
2 个月之前
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
YouTube
Chip Logic Studio
已浏览 1521 次
2 个月之前
0:59
Verilog lecture 1 || Verilog HDL by Samir palnitkar || || How to learn Verilog #verilog
YouTube
Aditya Singh
已浏览 572 次
2 个月之前
Verilog Coding Examples
2:55
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
YouTube
Chip Logic Studio
已浏览 101 次
2 个月之前
1:00
Timescale directive in verilog ||Verilog Coding techniques in verilog || #allaboutvlsi
YouTube
ALL ABOUT VLSI
已浏览 928 次
2 个月之前
0:52
Verilog coding techniques - part 8 || All about VLSI ||
YouTube
ALL ABOUT VLSI
已浏览 2083 次
2 个月之前
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 164 次
2 个月之前
YouTube
Chip Logic Studio
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
已浏览 1521 次
2 个月之前
YouTube
Chip Logic Studio
0:59
Verilog lecture 1 || Verilog HDL by Samir palnitkar || || How to learn Verilog #verilog
已浏览 572 次
2 个月之前
YouTube
Aditya Singh
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
已浏览 1907 次
1 个月前
YouTube
Cadence Design Systems
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 100 次
2 个月之前
YouTube
Chip Logic Studio
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 116 次
2 个月之前
YouTube
Chip Logic Studio
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 83 次
2 个月之前
YouTube
Chip Logic Studio
2:55
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
已浏览 101 次
2 个月之前
YouTube
Chip Logic Studio
1:00
Timescale directive in verilog ||Verilog Coding techniques in verilog || #allaboutvlsi
已浏览 928 次
2 个月之前
YouTube
ALL ABOUT VLSI
0:52
Verilog coding techniques - part 8 || All about VLSI ||
已浏览 2083 次
2 个月之前
YouTube
ALL ABOUT VLSI
0:44
Common coding mistakes in verilog part - 6
已浏览 1984 次
2 个月之前
YouTube
ALL ABOUT VLSI
0:25
Want to know how a 7-segment HEX display works on an FPGA? 🔢 In this short demo, I’ll show you how 4 binary switches can display numbers and letters (0–F) on the 7-segment display using Verilog. 👉 Watch the full tutorial on my channel (check my bio) for the complete step-by-step explanation and code! #engineer #programming #learnfpga #fpga #verilog
已浏览 161 次
9 个月之前
TikTok
chipcraftfpga
0:10
Desenvolvimento de Tecnologias e Programação: O Futuro
已浏览 8万 次
2023年3月14日
TikTok
easycody
0:16
Brushless Motor PCBA Printing and Assembly
已浏览 4.3万 次
2023年4月8日
TikTok
whatsapp8613576105646
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a search engine for recruiters—if your profile doesn’t have the right keywords, you won’t be found or considered for interviews. To fix this, you need to: 🔑 Target Keywords: Add technical skills like (ex. Python, Verilog, or UVM) to your headline, about section, and experience. 🖼️ Build a Portfolio: Don’t just list skills—post photos of your hardware builds or screen recordings of your code. 📄 Pin Your Resume
已浏览 3966 次
5 个月之前
TikTok
engcalebj28
Servomotor con FPGA NANO 1k: Proyecto Mecatrónico
已浏览 6245 次
10 个月之前
TikTok
fpgaedudesign
0:35
FPGAs Peruanas: Prototipo Oficial y Entrenamiento
已浏览 1.1万 次
2024年11月12日
TikTok
capsula.electronica
0:48
Opiniones sobre el autoroute en Altium para FPGA
已浏览 9776 次
2024年12月17日
TikTok
capsula.electronica
0:10
4 fpga stratosky rumbo a Mexico #Stratosky #verilog #systemverilog #fpga #vhdl
已浏览 1630 次
4 个月之前
TikTok
capsula.electronica
展开
更多类似内容
反馈